Dashboard PE Power Exam Prep Power Electronics & Controls Converters & rectifiers Rectifier waveforms — half-wave, full-wave, 3-φ 6-pulse, SCR control

Rectifier waveforms — half-wave, full-wave, 3-φ 6-pulse, SCR control

V_dc equations, ripple factor, firing-angle control, and 6-pulse line-current harmonics (5th, 7th, 11th, 13th).

Sophomore ~11 min

Step 1 — Single-phase half-wave: 1 diode, V_dc = V_m / π ≈ 0.318·V_m

0.55×
V_dc ripple α

Reference notes

Use Next → on the narrator above to walk through five rectifier topologies plus their ripple, harmonic, and firing-angle behaviour.

Rectifier output equations (no filter)

TopologyV_dc / V_mRipple factorf_ripple / f_line
1-φ half-wave (1 diode)1/π ≈ 0.3181.21 (121 %)1
1-φ full-wave bridge (4 diodes)2/π ≈ 0.6370.482 (48 %)2
3-φ half-wave (3 diodes, 3-pulse)3√3 / (2π) ≈ 0.8270.183 (18 %)3
3-φ full-wave bridge (6 diodes, 6-pulse)3√3 / π ≈ 1.654 (V_LN peak basis)
or 3/π · V_LL,peak ≈ 1.35 · V_LL,RMS
0.042 (4.2 %)6
12-pulse (two 6-pulse, 30° shift)Same as 6-pulse~0.010 (1.0 %)12

More pulses → smoother DC, smaller filter capacitor, and cleaner line current.

Thyristor (SCR) firing-angle control

Replace each diode with a thyristor (SCR) and delay its turn-on by firing angle α (measured from the natural commutation point). The DC output scales as:

Vdc = Vdc,max · cos α

SCR converters dominated industrial DC drives until the 1990s. Today they're used in HVDC line-commutated converters and very large drives (rolling mills, etc.); IGBT-based PWM converters have replaced them in most applications below a few megawatts.

Line-current harmonics

A non-controlled rectifier draws line current only when its diodes conduct — typically a square-shaped pulse per phase per half-cycle. The Fourier decomposition of this current gives harmonics at specific orders:

Total harmonic distortion (THD) for a bare 6-pulse VFD line current is typically 25–35 %. IEEE Std 519 sets allowable limits depending on the short-circuit ratio (I_sc / I_load) at the point of common coupling — typically 5 % total or less. Mitigation:

Worked example: VFD DC-bus voltage

A 6-pulse VFD fed by a 480 V (V_LL,RMS) supply has a DC-bus voltage:

VDC,bus = 1.35 · VLL,RMS = 1.35 · 480 ≈ 648 V

(In practice the DC bus voltage drops slightly under load due to line/transformer impedance and DC-bus capacitor ripple; nominal is 650 V.)

Take-away. V_dc for the 6-pulse bridge is the workhorse equation: V_dc = 3·V_LL,peak / π ≈ 1.35 · V_LL,RMS. Ripple factor drops dramatically with more pulses — 121 % (1-φ HW) → 48 % (1-φ FW) → 18 % (3-φ HW) → 4.2 % (3-φ FW / 6-pulse). SCR bridges add V_dc = V_dc,max · cos α, with α > 90° entering inverter mode. 6-pulse line harmonics are 6n ± 1 (5, 7, 11, 13...); 12-pulse cancels the 5th and 7th.

Keyboard shortcuts